External 10MHz clock question: Sample clock

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Conrad_PA5Y
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External 10MHz clock question: Sample clock

Postby Conrad_PA5Y » Sat Jul 07, 2018 7:31 pm

Hello all.

When an external 10MHz clock is used is the 122.8 MHz clock locked to the 10MHz clock using an FPGA based PLL or is the 122.8 MHz Xtal no longer used and the sample clock generated with by a multiplier?

73

Conrad PA5Y
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w-u-2-o
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Re: External 10MHz clock question: Sample clock

Postby w-u-2-o » Sat Jul 07, 2018 9:01 pm

The 122.8 MHz crystal is always used and all clocks are generated and locked the same way, regardless of whether the 10MHz reference is internal or external.

The hardware design alone shows this, as the firmware does not know where the 10MHz reference is sourced from, i.e. there is no hardware input to the FPGA that is associated with reference source location.
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Conrad_PA5Y
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Re: External 10MHz clock question: Sample clock

Postby Conrad_PA5Y » Sun Jul 08, 2018 1:08 pm

OK so that must mean that the 128.8 MHz clock must be 'compared' to the 10 MHz reference at all times irrespective of it's source. I am trying to determine the merit of a fitting better quality 122.8 MHz (lower PN) sample clock oscillator. The two clocks must be locked in some way otherwise what is the point of the reference clock? If there is an internal PLL there is probably no point changing the 128.8 MHz oscillator.

I have not been able to find a good explanation of how the 10 MHz and 128.8 MHz clocks are locked.

73

Conrad PA5Y
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w-u-2-o
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Re: External 10MHz clock question: Sample clock

Postby w-u-2-o » Sun Jul 08, 2018 4:06 pm

Again, all you need to do is refer to the schematic. The 122.88MHz oscillator is a VCXO, a Crystek CVHD-950 if memory serves. The voltage on the control pin is provided by the output of a PLL that is instantiated in the FPGA firmware and which is locked to the 10MHz reference.

I'm not 100% sure of the path from the VCXO to the FPGA. It would appear that the FPGA relies on the clock output of the ADC to close the loop. One would have to inspect firmware source code, freely available at the TAPR Github repository, to understand the PLL design in detail.
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Conrad_PA5Y
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Re: External 10MHz clock question: Sample clock

Postby Conrad_PA5Y » Sun Jul 08, 2018 5:49 pm

Alternatively as is normal practice a block diagram of the clock regime could have been provided. This gives unambiguous information. Why should a user be expected to consult schematics and even worse source code? Even my TS2000 manual has this information. In fact I probably do not have the ability to understand the source code unless it is extremely well commented. I should not have to do this. I do understand the schematics but again would expect more high level diagrams. Time is very precious to me and is spread thinly enough.

This project is held together with string and chewing gum. Fair enough some of it is very good quality chewing gum but I do wish that this kind of basic information was provided.

As you know Scott I do not accept many of your 'allowances' and expect more in certain areas. Of course I accept that voluntary work will never be documented like a professional project or application but I feel that the hardware manufacturer shows insufficient diligence in this area. I will remain critical of Apache until they document the hardware that they sell as a complete radio. That is the tone of their adverts but it is emphatically NOT the reality. For me with a 100D the ship has sailed so I will have to rely on you and a few others to fill in the gaps,

Regards

Conrad PA5Y
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w-u-2-o
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Re: External 10MHz clock question: Sample clock

Postby w-u-2-o » Sun Jul 08, 2018 8:42 pm

I have to agree with you, Conrad, the tone of the ad copy definitely leads one to believe the actual experience in terms of documentation and support will be more akin to a mainstream radio brand than it is. I, too, was somewhat disappointed at the start. Heck, right out of the box I had the classic "PC cannot find the radio" problem, followed immediately by the "Oh my god, this spectral display looks terrible, where are all the signals, what have I got myself into?" moment. PureSignal was brand new and few people understood how to use it much less explain how to use it. I certainly didn't understand the relationship between Apache and the open source community.

Obviously, if you do figure it out, these radios are among the best out there, with features and capabilities no other radios have. But it sure isn't easy sometimes.

Nevertheless, I was enjoying my radio so much, in between occasionally frustrating periods when I couldn't figure something out or when a new version of software broke something, that I wanted to help out with the open source portion of the radio. Unfortunately I am not a software or firmware developer, nor in the employ of Apache, just a plain old regular user. So I try to help out by answering questions. Sometimes the information is simply not there. Sometimes it is there but in an inconvenient form. I thought about writing a book or manual, but I don't have that kind of time, either, just like you.. And I certainly don't have all the answers or all the experiences.

Anyhow, as more people become more experienced with the platforms and the architecture, I hope between all of us we'll be able to answer nearly any question posed on the forum or mailing list because that's really the only resources there are beyond the somewhat limited manual.

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