where is J14 on Angelia board

marc
Posts: 34
Joined: Mon May 15, 2017 2:40 pm

where is J14 on Angelia board

Postby marc » Sun Oct 28, 2018 12:02 pm

Hi
I'm looking for the equivalent of the Hermes J14 connector on the Angelia and Orion board (pin 2 precisely). Or more exactly, the connector dedicated to the PWM "EER output" on new generation boards.

If someone allready has this answer... I know, I'm lazzy, but asking is easier than digging in the FPGA code, as I'm definitely not (and probably never be) a vhdl programmer.
73'
Marc f6itu
User avatar
w-u-2-o
Posts: 5539
Joined: Fri Mar 10, 2017 1:47 pm

Re: where is J14 on Angelia board

Postby w-u-2-o » Sun Oct 28, 2018 1:22 pm

I just dug into the Angelia v6.0 code for you, and can find no evidence of any EER support at all. Nowhere in the code is reference made to "EER" or "envelope". There are references to "PWM", but those are all associated with other things, not EER.

Here are all the internal signal assignments:

Code: Select all

module Angelia(
   //clock afc
  input _122MHz,                 //122.88MHz from VCXO
  input  OSC_10MHZ,              //10MHz reference in
  output FPGA_PLL,               //122.88MHz VCXO contol voltage

  //attenuator (DAT-31-SP+)
  output ATTN_DATA,              //data for input attenuator
  output ATTN_DATA_2,
  output ATTN_CLK,               //clock for input attenuator
  output ATTN_CLK_2,
  output ATTN_LE,                //Latch enable for input attenuator
  output ATTN_LE_2,

  //rx adc (LTC2208)
  input  [15:0]INA,              //samples from LTC2208
  input  [15:0]INA_2,            //samples from LTC2208 #2
  input  LTC2208_122MHz,         //122.88MHz from LTC2208_122MHz pin
  input  LTC2208_122MHz_2,       //122.88MHz from #2 LTC2208_122MHz pin
  input  OVERFLOW,               //high indicates LTC2208 have overflow
  input  OVERFLOW_2,             //high indicates LTC2208 have overflow
  output RAND,            //high turns ramdom on
  output RAND_2,          //high turns ramdom on
  output PGA,            //high turns LTC2208 internal preamp on
  output PGA_2,          //high turns LTC2208 internal preamp on
  output DITH,            //high turns LTC2208 dither on
  output DITH_2,          //high turns LTC2208 dither on
  output SHDN,            //x shuts LTC2208 off
  output SHDN_2,          //x shuts LTC2208 off

  //tx adc (AD9744ARU)
   output reg  DAC_ALC,           //sets Tx DAC output level
  output reg signed [13:0]DACD,  //Tx DAC data bus
 
  //audio codec (TLV320AIC23B)
  output CBCLK,               
  output CLRCIN,
  output CLRCOUT,
  output CDIN,                   
  output CMCLK,                  //Master Clock to TLV320
  output CMODE,                  //sets TLV320 mode - I2C or SPI
  output nCS,                    //chip select on TLV320
  output MOSI,                   //SPI data for TLV320
  output SSCK,                   //SPI clock for TLV320
  input  CDOUT,                  //Mic data from TLV320 
 
  //phy rgmii (KSZ9021RL)
  output [3:0]PHY_TX,
  output PHY_TX_EN,              //PHY Tx enable
  output PHY_TX_CLOCK,           //PHY Tx data clock
  input  [3:0]PHY_RX,     
  input  RX_DV,                  //PHY has data flag
  input  PHY_RX_CLOCK,           //PHY Rx data clock
  input  PHY_CLK125,             //125MHz clock from PHY PLL
  input  PHY_INT_N,              //interrupt (n.c.)
  output PHY_RESET_N,
  input  CLK_25MHZ,              //25MHz clock (n.c.) 
 
   //phy mdio (KSZ9021RL)
   inout  PHY_MDIO,               //data line to PHY MDIO
   output PHY_MDC,                //2.5MHz clock to PHY MDIO
 
   //eeprom (25AA02E48T-I/OT)
   output    SCK,                      // clock on MAC EEPROM
   output    SI,                     // serial in on MAC EEPROM
   input      SO,                      // SO on MAC EEPROM
   output     CS,                     // CS on MAC EEPROM
   
  //eeprom (M25P16VMW6G) 
  output NCONFIG,                //when high causes FPGA to reload from eeprom EPCS16   
 
  //12 bit adc's (ADC78H90CIMT)
  output ADCMOSI,               
  output ADCCLK,
  input  ADCMISO,
  output nADCCS,
 
  //alex/apollo spi
  output SPI_SDO,                //SPI data to Alex or Apollo
  input  SPI_SDI,                //SPI data from Apollo
  output SPI_SCK,                //SPI clock to Alex or Apollo
  output J15_5,                  //SPI Rx data load strobe to Alex / Apollo enable
  output J15_6,                  //SPI Tx data load strobe to Alex / Apollo ~reset
 
  //misc. i/o
  input  PTT,                    //PTT active low
  input  KEY_DOT,                //dot input from J11
  input  KEY_DASH,               //dash input from J11
  output FPGA_PTT,               //high turns Q4 on for PTTOUT
  input  MODE2,                  //jumper J13 on Angelia, 1 if removed
  input  ANT_TUNE,               //atu
  output IO1,                    //high to mute AF amp   
  input  IO2,                    //PTT, used by Apollo
 
  //user digital inputs
  input  IO4,                   
  input  IO5,
  input  IO6,
  input  IO8,
 
  //user outputs
  output USEROUT0,               
  output USEROUT1,
  output USEROUT2,
  output USEROUT3,
  output USEROUT4,
  output USEROUT5,
  output USEROUT6,
 
    //debug led's
  output Status_LED,     
  output DEBUG_LED1,             
  output DEBUG_LED2,
  output DEBUG_LED3,
  output DEBUG_LED4,
  output DEBUG_LED5,
  output DEBUG_LED6,
  output DEBUG_LED7,
  output DEBUG_LED8,
  output DEBUG_LED9,
  output DEBUG_LED10,
 
   // RAM
  output wire RAM_A0,
  output wire RAM_A1,
  output wire RAM_A2,
  output wire RAM_A3,
  output wire RAM_A4,
  output wire RAM_A5,
  output wire RAM_A6,
  output wire RAM_A7,
  output wire RAM_A8,
  output wire RAM_A9,
  output wire RAM_A10,
  output wire RAM_A11,
  output wire RAM_A12,
  output wire RAM_A13 
);
marc
Posts: 34
Joined: Mon May 15, 2017 2:40 pm

Re: where is J14 on Angelia board

Postby marc » Mon Oct 29, 2018 11:04 am

Thank you Scott

Hope this function/gpio hasn't been deliberately suppressed on the new hardware.
Anyhow, the software part is still present in all configurations of PowerSDR mRX (DSP tab)

Thanks a lot for the time you spent ... I'll keep on digging :-)
73'
Marc f6itu

..some minutes later...

I confirm : no mention of EER in the Angelia or Orion firmware changelog (only in the Hermes section
https://github.com/TAPR/OpenHPSDR-Firmw ... 201/Hermes
). I have some Quartus feedling to do to understand.
The strict equivalent gpio is not even used or connected (E3), implying some mods of the code to have an accessible fpga pin.
I thought the Hermes board/frmwr was considered as the "least common multiple" of the OpenHPSDR dev group. :- (

Anyhow, I'm pretty sure a workaround is not impossible.
Thks again... I learned something new today :- D

Marc f6itu
User avatar
w-u-2-o
Posts: 5539
Joined: Fri Mar 10, 2017 1:47 pm

Re: where is J14 on Angelia board

Postby w-u-2-o » Mon Oct 29, 2018 2:54 pm

Marc,

It might be best to drop Phil a direct line, see what's up with this.

73,

Scott

P.S. it's a few minutes work to install Quartus Lite, and a few more minutes to learn how to import .qar files, but I've found it helpful and, once installed, easy to do.

It's really quite interesting to see how few lines of code are actually involved in the design.
marc
Posts: 34
Joined: Mon May 15, 2017 2:40 pm

Re: where is J14 on Angelia board

Postby marc » Mon Oct 29, 2018 7:03 pm

You're absolutely right, Scott

As I allready said, I'm lazzy. Quartus is installed for quite a long time on my "Hermes lite" computer... and I didn't had the time to do the same on my main machine. It's done now

... and I took the time to browse all available firmwares. Without any doubt now, EER exists only in the Hermes frmw (and the verilog is clear and easy to read... I didn't expect that).

I won't bother Phil in the immediate future. I intend to use my Hermes Lite V2.x for the first tests (less financial risks compared with my angelia) and it will certainly take 3 to 4 months just to fully understand the many papers, talks and technical communications made by DJ1MR on the E.T. and EER subject.

In other words, quite a lot of pcb prototypes to etch and many transistors to burn before asking Phil to add EER on newer boards.

I should admit, I was conviced that all firmwares where approximately the same, and it would not have occurred to me that the oldest platform was the only one that included such an important and intersting feature.
Also surprised to see that this question has never been raised before by 100D, 200D, 7000 or 8000 users.

Even if all that does not come to anything, I would have learned a lot of things

73'
Marc f6itu

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